1. Technical Field
The present disclosure relates to a package structure, in particular, to a stacked chip package structure.
2. Description of Related Art
Three-dimensional integrated circuit (3D IC) refers to vertically stacked chips connected by through-silicon via (TSV) technology, which shortens the connections between the stacked chips, reduces the sizes of the device or package and improves the operation band width. The design of 3D integrated circuit can effectively increase the product performance, lower the power consumption and costs, miniaturize the size and integrate hetero-integrated circuit.
For 3D integrated circuits incorporated with through-silicon via technology, the distance between the stacked chips becomes very small, probably less than 100 microns, and the reliability issue becomes significant following the tight arrangement of solder balls. Smaller pitch of the solder balls means smaller joint area of the solder balls. Compared with the typical large solder balls, the mechanical stress induced by fatigue and thermal cycling is concentrated within a smaller area of the solder joint, and if not properly treated, the breakage of the solder joint may occur.
The solution is to apply underfill under the chip or surface mounting device. Although the underfill may fill the gap between the integrated circuit and the carrying substrate, how to dispense the underfill between the stacked chips effectively and efficiently is an issue.